Potato Processor

Control Registers

Control and status registers (CSRs) are accessed using the following assembly code instructions:

csrrw dest, csr, src

- writes the value of the register src into a CSR and places the old value in dest.

csrrs dest, csr, src

- sets bits in a CSR - does an or operation between src and csr and writes the result into the CSR. The old value of the CSR is placed in dest.

csrrc dest, csr, src

- clears bits in a CSR - does a and between the inverted value of src and csr and writes the result into the CSR. the old value of the CSR is placed in dest.

Immediate variants of the instructions also exist, csrrwi, csrrsi, and csrrci, replacing the source register with a 5-bit immediate value.

In addition, pseudo-instructions can be used in assembly code to read CSRs without specifying a new value for the register and to write CSRs while discarding the old value of the register. These instructions are csrr dest, csr and csrw csr, src.

Additional details of these instructions can be found in the RISC-V Privileged ISA Specification.

Implemented CSRs

The following control and status registers are available from code running on the Potato processor.

MCPUID

- Provides information about available CPU features.

MIMPID

- Provides information identifying the implementer of the processor.

MHARTID

- Hardware thread ID. If multiple instances of the processor is used in the same system, this register can be used to provide an application information about which processor it is currently running on.

MSCRATCH

- Scratchpad register. This register can be used without restriction.

MEPC

- Address at which an exception occurred. This register provides the address which is jumped to when an eret instruction is executed.

MTVEC

- Address of the exception vector. The default value of this register is 0x100. Note that machine mode traps and interrupts are taken from the address of this register plus 0xc0, making the address of the machine mode exception handler 0x1c0 when this register has its default value.

MTDELEG

- Unsupported, read as zero, writes ignored.

MIP

- Interrupts pending register. The upper 8 bits contains the status of the 8 IRQ inputs. Bit 7 contains the status of the internal timer interrupt and bit 3 contains the status of the software interrupt bit.

MIE

- Interrupt enable register. The bits of this register correspond to the bits of the MIP register. To enable an interrupt, set the corresponding bit to 1. Setting the software interrupt bit (bit 3) immediately causes a software interrupt to occur.

MBADADDR

- Address that caused a instruction or data load/store error.

MCAUSE

- Exception cause. Values for this register is provided further down.

MTIME

- Internal time counter value.

MTIMECMP

- Value to compare against MTIME to trigger the timer interrupt.

MSTATUS

- Status register. Only two bits of this register is used in the Potato processor; bit 0 is the master interrupt enable bit, while bit 3 stores the previous value of the master interrupt enable bit when an exception is taken. When an eret instruction is executed, the value of bit 3 is copied into bit 0.

The RISC-V Supervisor ISA Specification provides additional details for many of these registers.